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R

F

R

G

V

OCM

INP

INM

CM

R

F

R

G

R

S

0.1mF

0.1mF

10mF

1mF

R

T

+3.3V

+5V

0.1mF

10mF

-

5V

THS4503

R

IN

R

IN

10 W

ADS5510

11-Bit / 125MSPS

POWER-SUPPLY SEQUENCE

AVDD

REFP

29

28

2kW

1 W

1

F

m

POWER-DOWN

ADS5510

SLAS499 – JANUARY 2007

Figure 27. Using the THS4503 with the ADS5510

The preferred power-up sequence is to ramp AVDD first, followed by DRVDD, including a simultaneous ramp of

AVDD and DRVDD. In the event that DRVDD ramps up first in the system, care must be taken to ensure that AVDD

ramps up within 10 ms. Optionally, it is recommended to put a 2-k

Ω resistor from REFP (pin 29) to AVDD as

shown in Figure 28. This helps to make the device more robust to power supply ramp-up timings.

Figure 28.

The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bit

throughout the serial programming interface. Using the reduced clock speed, power-down may be initiated for

clock frequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to

device.

Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state and

only the internal reference remains on to reduce the power-up time. The power-down mode reduces power

dissipation to approximately 180 mW.

21

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