APPLICATION INFORMATION

Theory of Operation

Input Configuration

500 W

500 W

Buffer

VCM

Buffer

1.6 pF

1.6pF

GND

S0293-01

AIN

AIN

AVDD5

AVDD5

ADS5463/5474/54RF63

GND

GND

~ 2.5 nH Bond Wire

~ 2.5 nH Bond Wire

~ 0.5pF

Package

~ 0.5pF

Package

~ 200fF

BondPad

~ 200fF

BondPad

ADS5463

ADS54RF63

SLAS515E – NOVEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com

The ADS5463/ADS54RF63 is a 12-bit, 500/550-MSPS, monolithic pipeline ADC. Its bipolar analog core operates

from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The

conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input

signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series

of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the

falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process

results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word,

coded in offset binary format.

The ADS5463 and ADS54RF63 are identical in the way they are used on a board. They differ in their maximum

sample rate and spectral performance versus frequency. A good study of the contour plots in Figure 25,

Figure 26, Figure 43, and Figure 44 demonstrate the spectral differences. The digital output characteristics are

the same except the ADS54RF63 has less restrictive timing parameters.

The analog input for the ADS5463/ADS54RF63 consists of an analog pseudo-differential buffer followed by a

bipolar transistor track-and-hold (see Figure 48). The analog buffer isolates the source driving the input of the

ADC from any internal switching and presents a high impedance to drive at high input frequencies, as compared

to an ADC without a buffered input. The input common mode is set internally through a 500-

Ω resistor connected

from 2.4 V to each of the inputs. This results in a differential input impedance of 1 k

Ω. The 0.5 pF of parasitic

package capacitance is before soldering.

Figure 48. Analog Input Equivalent Circuit (unsoldered)

For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swing

symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal

swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable, with

the characteristics of performance versus input amplitude demonstrated in Figure 16 and Figure 17. For

instance, for performance at 1.1 VPP rather than 2.2 VPP, see the SNR and SFDR at -6 dBFS (0 dBFS = 2.2 VPP).

The maximum swing is determined by the internal reference voltage generator, eliminating the need for any

external circuitry for this purpose.

26

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