ADS5295IPFP datasheet(7/93 Pages) TI2

7 / 93 page

ADS5295

www.ti.com

SBAS595 – DECEMBER 2012

TIMING REQUIREMENTS

(1)

Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, sampling frequency = 100 MSPS, sine-wave input clock, CLOAD =

5 pF, and RLOAD = 100 Ω, unless otherwise noted.

Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and

LVDD = 1.7 V to 1.9 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

Aperture delay matching

Between any two channels of the same device

±200

Between two devices at the same temperature and

Variation of aperture delay

±1

LVDD supply

Aperture jitter

Sample uncertainty

320

fs rms

Time to valid data after coming out of standby

µs

Wake-up time

Time to valid data after coming out of global power-

100

µs

down mode

One-wire LVDS Output interface

Clock cycles

ADC latency(2)

Two-wire LVDS Output interface

Clock cycles

TWO-WIRE, 12x SERIALIZATION

tSU

Data setup time

Data valid to zero-crossing of LCLKP

0.52

Data hold time

Zero-crossing of LCLKP to data becoming invalid

0.62

tPDI =

Input clock rising edge crossover to output clock

(11/12)

tPDI

Clock propagation delay

rising edge crossover

× tS +

tDELAY

Delay time

8.5

13.5

Duty cycle of differential clock

LVDS bit clock duty cycle

(LCLKP – LCLKN)

ACROSS ALL SERIALIZATION MODES

Rise time measured from –100 mV to +100 mV,

tFALL

Data fall time

0.11

10 MSPS

≤ sampling frequency ≤ 100 MSPS

Rise time measured from –100 mV to +100 mV,

tRISE

Data rise time

0.11

10 MSPS

≤ sampling frequency ≤ 100 MSPS

Rise time measured from –100 mV to +100 mV,

tCLKRISE

Output clock rise time

0.11

10 MSPS

≤ sampling frequency ≤ 100 MSPS

Rise time measured from –100 mV to +100 mV,

tCLKFALL

Output clock fall time

0.11

10 MSPS

≤ sampling frequency ≤ 100 MSPS

(1)

Timing parameters are ensured by design and characterization, but are not tested in production.

(2)

At higher frequencies, tPDI is greater than one clock period and the overall latency = ADC latency + 1.

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