TMS320DM647 datasheet(156/167 Pages) TI

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6.21.3 VLYNQ Electrical Data/Timing

VCLK

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372A – MAY 2007 – REVISED JUNE 2007

Table 6-77. VLYNQ Registers (continued)

HEX ADDRESS RANGE

ACRONYM

0x3800 00C0

RCHIPVER

VLYNQ Remote Chip Version Register

0x3800 00C4

RAUTNGO

VLYNQ Remote Auto Negotiation Register

0x3800 00C8

RMANNGO

VLYNQ Remote Manual Negotiation Register

0x3800 00CC

RNGOSTAT

VLYNQ Remote Negotiation Status Register

0x3800 00D0 - 0x3800 00DC

Reserved

0x3800 00E0

RINTVEC0

VLYNQ Remote Interrupt Vector 3 - 0

0x3800 00E4

RINTVEC1

VYLNQ Remote Interrupt Vector 7 - 4

0x3800 00E8 - 0x3800 00FC

Reserved for future use [Remote Interrupt Vectors 8 - 31]

Table 6-78. Timing Requirements for VCLK for VLYNQ (see Figure 6-44)

-720

-900

NO.

UNIT

MIN

MAX

tc(VCLK)

Cycle time, VCLK

tw(VCLKH)

Pulse duration, VCLK high

tw(VCLKL)

Pulse duration, VCLK low

tt(VCLK)

Transition time, VCLK

Figure 6-44. VCLK Timing for VLYNQ

Peripheral Information and Electrical Specifications

156

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