L99VR02XP datasheet(49/50 Pages) STMICROELECTRONICS

49 / 50 page

Figure 51.

Power-up when LDO2 is tracker of LDO1................................................. 32

Figure 52.

Power-up when LDO2 is tracker of external regulator ........................................ 33

Figure 53.

Detracking timing diagram in case of UV ................................................. 34

Figure 54.

Detracking timing diagram in case of OV ................................................. 35

Figure 55.

Detracking timing diagram in case of thermal fault........................................... 36

Figure 56.

Undervoltage lock out on output voltage.................................................. 37

Figure 57.

Typical application................................................................. 38

Figure 58.

PowerSSO-36 on two-layers PCB (2s0p to JEDEC JESD 51-5) ................................. 39

Figure 59.

PowerSSO-36 on four-layers PCB (2s2p to JEDEC JESD 51-7) ................................. 40

Figure 60.

PowerSSO-36 thermal resistance junction to ambient vs PCB 4 layer copper area .................... 40

Figure 61.

PowerSSO-36 thermal impedance junction to ambient vs PCB copper area ......................... 40

Figure 62.

Thermal fitting model of a Vreg in PowerSSO-36............................................ 41

Figure 63.

PowerSSO-36 (exposed pad down) package outline ......................................... 42

Figure 64.

PowerSSO-36 tape and reel shipment ................................................... 44

L99VR02XP

List of figures

DS14686 - Rev 1

page 49/50

L99VR02XP bảng dữ liệu(PDF) 49 Page - STMicroelectronics