DLP391TPFSB datasheet(5/46 Pages) TI2

5 / 46 page

Table 4-1. Pin Functions (continued)

PIN (2)

TYPE(1)

DESCRIPTION

TERMINATION

TRACE

LENGTH

(mm)

NAME

PAD ID

D_DP(7)

K22

High-Speed Differential Data Pair lane D7

Differential 100Ω

1.406

D_DN(7)

K21

High-Speed Differential Data Pair lane D7

Differential 100Ω

1.881

DCLK_DP

K19

High-Speed Differential Clock D

Differential 100Ω

3.916

DCLK_DN

K18

High-Speed Differential Clock D

Differential 100Ω

4.022

TEMP_N

Temp Diode N

1.133

TEMP_P

Temp Diode P

1.237

LS_RDATA_D

LPSDR Output

4.978

LS_RDATA_C

LPSDR Output

2.897

LS_WDATA

LPSDR Input

2.524

LS_RDATA_B

LPSDR Output

5.103

LS_RDATA_A

LPSDR Output

1.725

LS_CLK

LPSDR Input

2.454

DMD_DEN_ARSTZ

ARSTZ

17.5kΩ pulldown

0.735

VDD

A6, A8, A10,

A12, A14,

A16, A18, B4,

B11, B13,

B15, B19,

B21, C21,

D22, E21, G4,

J1, J4, J6, L2,

M15

Digital Core Supply Voltage

8.350

VBIAS

A20, B6

Supply Voltage for Positive Bias of Micromirror

reset signal

7.409

VRESET

B8, B17

Supply Voltage for Negative Bias of

Micromirror reset signal

3.374

VOFFSET

B9, M16

Supply voltage for HVCMOS logic,stepped up

logic level

1.797

VDDI

C22, E4, F2,

G20, J2,L22

19.977

VSS

A9, A11, A13,

A15, A17,

A19, B3, B10,

B12, B14,

B16, B18,

B20, C1, C6,

D4, D19, E22,

F3, F6, G19,

H4, H19, H22,

J3, J5, J20,

K2, K20, L3,

L6, L18, L21,

Ground

12.614

N/C

A21, C23,

K23, L23,

M23

No Connect Pin

N/A

(1)

I=Input, O=Output, P=Power, G=Ground, NC=No Connect

(2)

Only 151 pins are electrically connected for functional use.

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DLP391TP

DLPS289A – JUNE 2025 – REVISED SEPTEMBER 2025

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