Page 1 of 7

www.siliconsupplies.com

Die Size (Unsawn)

760 x 560

30 x 22

µm

mils

Minimum Bond Pad Size

70 x 70

2.76 x 2.76

µm

mils

Die Thickness

280 (±20)

11.02 (±0.79)

µm

mils

Top Metal Composition

Al-Si-Cu

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC4040

12-Stage Binary Ripple Counter in bare die form



Output Drive Capability: 10 LSTTL Loads



Low Input Current: 1µA



Outputs directly interface CMOS, NMOS and TTL



Operating Voltage Range: 2V to 6V



CMOS High Noise Immunity



Function compatible with CD4040B



Full Military Temperature Range.

Rev 1.0

15/09/25

Features:

The following part suffixes apply:



No suffix - MIL-STD-883 /2010B Visual Inspection



“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT



“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification



Default – Die in Waffle Pack (400 per tray capacity)



Sawn Wafer on Tape – On request



Unsawn Wafer – On request



Die Thickness <> 280µm(11 Mils) – On request



Assembled into Ceramic Package – On request

The 54HC4040 is fabricated using an advanced 5V CMOS

process to combine high speed LSTTL performance with

CMOS low power. The device is a 12-stage asynchronous

binary counter with a clock input, an overriding

asynchronous master reset input and twelve parallel

outputs (Q1 to Q12). A high-to-low transition on the clock

input increments the counter. The active–high reset clears

all counter stages and forces all outputs low, independent of

clock state. Device inputs include clamp diodes that enable

the use of current limiting resistors to interface inputs to

voltages in excess of VCC.

Description

Die Dimensions in µm (mils)

760 (30)

Ordering Guide