OUT

IN

GND PLANE

Represents via used for application

specific connections

1

2

3

4

C

IN

C

OUT

EN

IN

GND

EN

OUT

N/C

CIN

COUT

1

2

3

4

5

VIN

GND

Enable

VOUT

GND

19

LP5907-Q1

www.ti.com

SNVSA34E – SEPTEMBER 2014 – REVISED DECEMBER 2019

Product Folder Links: LP5907-Q1

Submit Documentation Feedback

Copyright © 2014–2019, Texas Instruments Incorporated

10 Layout

10.1 Layout Guidelines

The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that

are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as

close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1

ground pin using as wide and short copper traces as are practical.

Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add

parasitic inductances and resistance that results in inferior performance especially during transient conditions

10.2 Layout Examples

Figure 23. LP5907MF-x.x (SOT-23) Typical Layout

Figure 24. Layout Example for the DQN Package