LP85571 datasheet(22/49 Pages) TI2

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Data Output

Transmitter

SCL

Start Condition

Data Output

By Receiver

3 - 6

Acknowledgement Signal

from Receiver

Transmitter Stays Off the

Bus During the

Acknowledgement Clock

LP8557, LP85571

SNVSA15B – DECEMBER 2013 – REVISED DECEMBER 2015

www.ti.com

Programming (continued)

Figure 35. Bus Acknowledge Cycle

8.5.1.5 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

8.5.1.6 Control Register Write Cycle

•

Master device generates start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master sends data byte to be written to the addressed register.

•

Slave sends acknowledge signal.

•

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

8.5.1.7 Control Register Read Cycle

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct.

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

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