LDO1

LDO2

VREF

POR

+

-

VIN

EN1

EN2

CBYP

GND

SET

POR

VOUT2

VOUT1

1 2A

LP3996

SNVS360D – NOVEMBER 2006 – REVISED OCTOBER 2013

www.ti.com

Functional Block Diagram

Pin Functions

Pin No

Symbol

Name and Function

1

VIN

Voltage Supply Input. Connect a 1 µF capacitor between this pin and GND.

2

EN1

Enable Input to Regulator 1. Active high input.

High = On. Low = OFF.

3

EN2

Enable Input to Regulator 2. Active high input.

High = On. Low = OFF.

4

CBYP

Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce output

noise and improve line transient and PSRR.

This pin may be left open.

5

SET

Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open,

there will be no delay.

6

GND

Common Ground pin. Connect externally to exposed pad.

7

N/C

No Connection. Do not connect to any other pin.

8

POR

Power-On Reset Output. Open drain output. Active low indicates under-voltage output on Regulator 2.

A pull-up resistor is required for correct operation.

9

VOUT2

Output of Regulator 2. 300 mA maximum current output. Connect a 1 µF capacitor between this pin

and GND.

10

VOUT1

Output of Regulator 1. 150 mA maximum current output. Connect a 1 µF capacitor between this pin

and GND.

Pad

GND

Common Ground. Connect to Pin 6.

2

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