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AD6653 bảng dữ liệu(PDF) 31 Page - Analog Devices

tên linh kiện AD6653
Giải thích chi tiết về linh kiện  IF Diversity Receiver
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AD6653 bảng dữ liệu(HTML) 31 Page - Analog Devices

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AD6653
Rev. 0 | Page 31 of 80
DIGITAL DOWNCONVERTER
The AD6653 includes a digital processing section that provides
filtering and reduces the output data rate. This digital processing
section includes a numerically controlled oscillator (NCO),
a half-band decimating filter, an FIR filter, and a second coarse
NCO (fADC/8 fixed value) for output frequency translation. Each
of these processing blocks (except the decimating half-band
filter) has control lines that allow it to be independently enabled
and disabled to provide the desired processing function. The
digital downconverter can be configured to output either real data
or complex output data. These blocks can be configured in five
recommended combinations to implement different signal
processing functions.
DOWNCONVERTER MODES
Table 14 details the recommended downconverter modes of
operation in the AD6653.
Table 14. Downconverter Modes
Mode
NCO/Filter
Output Type
1
Half-band filter only
Real
2
Half-band filter and FIR filter
Real
3
NCO and half-band filter
Complex
4
NCO, half-band filter, and FIR filter
Complex
5
NCO, half-band filter, FIR filter, and
fADC/8 NCO
Real
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation is accomplished with an NCO. Each of
the two processing channels shares a common NCO. Amplitude
and phase dither can be enabled on chip to improve the noise and
spurious performance of the NCO. A phase offset word is available
to create a known phase relationship between multiple AD6653s.
Because the decimation filter prevents usage of half the Nyquist
spectrum, a means is needed to translate the sampled input
spectrum into the usable range of the decimation filter. To
achieve this, a 32-bit, fine tuning, complex NCO is provided.
This NCO/mixer allows the input spectrum to be tuned to dc,
where it can be effectively filtered by the subsequent filter
blocks to prevent aliasing.
HALF-BAND DECIMATING FILTER AND FIR FILTER
The goal of the AD6653 digital filter block is to allow the sample
rate to be reduced by a factor of 2 while rejecting aliases that fall
into the band of interest. The half-band filter is designed to operate
as either a low-pass or high-pass filter and to provide greater
than 100 dB of alias protection for 22% of the input rate of the
structure. For an ADC sample rate of 150 MSPS, this provides
a maximum usable bandwidth of 16.5 MHz when using the filter
in real mode (NCO bypassed) or a maximum usable bandwidth
of 33.0 MHz when using the filter in the complex mode (NCO
enabled).
The optional fixed-coefficient FIR filter provides additional
filtering capability to sharpen the half-band roll-off to enhance
the alias protection. It removes the negative frequency images
to avoid aliasing negative frequencies for real outputs.
fADC/8 FIXED-FREQUENCY NCO
A fixed fADC/8 NCO is provided to translate the filtered, decimated
signal from dc to fADC/8 to allow a real output. Figure 66 to
Figure 69 show an example of a 20 MHz input as it is processed
by the blocks of the AD6653.
–50
–24
–14
14
24
50
–4
4
0
Figure 66. Example AD6653 Real 20 MHz Bandwidth Input Signal Centered at
14 MHz (fADC = 100 MHz)
–50
–38
–28
0
10
50
–18 –10
Figure 67. Example AD6653 20 MHz Bandwidth Input Signal Tuned to
DC Using the NCO (NCO Frequency = 14 MHz)
–50
–38
–28
0
10
50
–18 –10
Figure 68. Example AD6653 20 MHz Bandwidth Input Signal with the
Negative Image Filtered by the Half-Band and FIR Filters
–50
0.25
22.5
12.5
50
Figure 69. Example AD6653 20 MHz Bandwidth Input Signal Tuned to
fADC/8 for Real Output



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