0.47 µF

0.1 µF

CP1

GND

CP2

VCP

VM

OUT1

ISEN

OUT2

OUT2

ISEN

OUT1

VM

VREF

I4

I3

I2

I1

I0

NC

ENBL

PHASE

DECAY

nFAULT

nSLEEP

VREF

GND

nRESET

V3P3OUT

0.1 µF

0.1 µF

0.1 µF

1 M

Ÿ

DRV8828

www.ti.com

SLVSA11G – OCTOBER 2009 – REVISED NOVEMBER 2015

10 Layout

10.1 Layout Guidelines

Each VM terminal must be bypassed to GND using a low-ESR ceramic bypass capacitors with recommended

values of 0.1

μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a

thick trace or ground plane connection to the device GND pin.

The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component may be an

electrolytic.

A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. TI recommends a value of 0.1

μF rated for VM . Place this component as close to the pins as possible.

A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.47

μF rated for 16 V. Place this component as close to the pins as possible. In addition, place a 1 MΩ between VM

and VCP.

Bypass V3P3OUT to ground with a ceramic capacitor rated 6.3 V. Place this bypassing capacitor as close to the

pin as possible.

The current sense resistor should be placed as close as possible to the device pins to minimize trace inductance

between the pin and resistor.

10.2 Layout Example

Figure 11. Example Layout

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