6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system

MIN

MAX

UNIT

TDMD

DMD storage temperature

–40

85

°C

TDP-AVG

Average dew point temperature, (non-condensing)(1)

24

°C

TDP-ELR

Elevated dew point temperature range, (non-condensing)(2)

28

36

°C

CTELR

Cumulative time in elevated dew point temperature range

6

Months

(1)

The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.

(2)

Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total

cumulative time of CTELR.

6.3 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

V

(1)

JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1) (2) (3)

MIN

NOM

MAX

UNIT

SUPPLY VOLTAGE RANGE(4)

VDD

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed interface

1.7

1.8

1.95

V

VDDI

Supply voltage for SubLVDS receivers

1.7

1.8

1.95

V

VOFFSET

Supply voltage for HVCMOS and micromirror electrode(5)

9.5

10

10.5

V

VBIAS

Supply voltage for mirror electrode

17.5

18

18.5

V

VRESET

Supply voltage for micromirror electrode

–14.5

–14

–13.5

V

|VDDI–VDD|

Supply voltage delta (absolute value)(6)

0.3

V

|VBIAS–VOFFSET| Supply voltage delta (absolute value)(7)

10.5

V

|VBIAS–VRESET|

Supply voltage delta (absolute value)(8)

33

V

CLOCK FREQUENCY

ƒclock

Clock frequency for low speed interface LS_CLK(9)

108

120

MHz

ƒclock

Clock frequency for high speed interface DCLK(10)

300

540

MHz

Duty cycle distortion DCLK

44%

56%

SUBLVDS INTERFACE(10)

| VID |

SubLVDS input differential voltage (absolute value) Figure 6-9, Figure 6-10

150

250

350

mV

VCM

Common mode voltage Figure 6-9, Figure 6-10

700

900

1100

mV

VSUBLVDS

SubLVDS voltage Figure 6-9, Figure 6-10

575

1225

mV

ZLINE

Line differential impedance (PWB/trace)

90

100

110

Ω

ZIN

Internal differential termination resistance Figure 6-11

80

100

120

Ω

100-Ω differential PCB trace

6.35

152.4

mm

ENVIRONMENTAL

TARRAY

Array Temperature – long-term operational(11) (12) (13) (14)

0

40 to

70(13)

°C

Array Temperature - short-term operational, 25 hr max(12) (15)

–20

-10

Array Temperature - short-term operational, 500 hr max(12) (15)

–10

0

Array Temperature – short-term operational, 500 hr max(12) (15)

70

75

|TDELTA|

Absolute Temperature difference between any point on the window edge and

the ceramic test point TP1 (16)

15

°C

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DLP4710LC

DLPS178C – MAY 2020 – REVISED JULY 2023

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