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CDCE706PW bảng dữ liệu(PDF) 26 Page - Texas Instruments

tên linh kiện CDCE706PW
Giải thích chi tiết về linh kiện  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER/MULTIPLIER/DIVIDER
PDF  46 Pages
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CDCE706PW bảng dữ liệu(HTML) 26 Page - Texas Instruments

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7dB
CenterSpread±0.4%
9
th
Harmonic,f =60
m
DownSpread3%
9
th
Harmonic,f =60
m
11.3dB
C001
SSC Modulation Amount
SSC Modulation Frequency
CDCE706
SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com
Figure 19. Spread-Spectrum Clocking With Center Spread and Down Spread
The peak amplitude of the modulated clock is 11.3 dB lower than the nonmodulated carrier frequency for down
spread and radiates less electromagnetic energy.
In SSC mode, the user can select the SSC modulation amount and SSC modulation frequency. The modulation
amount is the frequency deviation relative to the carrier (min/max frequency), whereas the modulation frequency
determines the speed of the frequency variation. In SSC mode, the maximum VCO frequency is limited to
167 MHz.
The CDCE706 supports center-spread modulation and down-spread modulation. In center spread, the clock is
symmetrically shifted around the carrier frequency and can be ±0.1%, ±0.25%, or ±0.4%. For down spread, the
clock frequency is always lower than the carrier frequency and can be 1%, 1.5%, 2%, or 3%. The down spread is
preferred if a system cannot tolerate an operating frequency higher than the nominal frequency (overclocking
problem).
Example:
Minimum
Center
Maximum
Modulation Type
Frequency
Frequency
Frequency
A
±0.25% center spread
53.865 MHz
54 MHz
54.135 MHz
B
1% down spread
53.46 MHz
—
54 MHz
C
0.5% down spread(1)
53.73 MHz
53.865 MHz
54 MHz
(1)
A down spread of 0.5% of a 54-MHz carrier is equivalent to 59.865 MHz at a center spread of ±0.25%.
The modulation frequency (sweep rate) can be selected between 30 kHz and 60 kHz. It is also based on the
VCO frequency as shown in the SSC Modulation Amount as shown in the Byte 25, Bits [6:4] table. As shown in
Figure 20, the damping increases with higher modulation frequencies. It may be limited by the tracking skew of a
downstream PLL. The CDCE706 uses a triangle modulation profile which is one of the common profiles for SSC.
26
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Copyright © 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE706



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