APPLICATION INFORMATION

SMBus Data Interface

Data Protocol

Slave Receiver Address (7 bits)

CDCE706

SCAS815I – OCTOBER 2005 – REVISED NOVEMBER 2008 ........................................................................................................................................... www.ti.com

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows

the SMBus specification Version 2.0, which is based on the principles of operation of I2C. More details of the

SMBus specification can be found at http://www.smbus.org.

Through the SMBus, various device functions, such as individual clock output buffers, can be individually

enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting on

power up; therefore, using this interface is optional. The clock device register changes are normally made on

system initialization, if any are required.

The clock-driver serial protocol accepts byte-write, byte-read, block-write, and block-read operations from the

controller.

For block-write/read operations, the bytes must be accessed in sequential order from lowest to highest byte

(most significant bit first) with the ability to stop after any complete byte has been transferred. For byte-write and

byte-read operations, the system controller can access individually addressed bytes.

Once a byte has been sent, it is written into the internal register and becomes effective immediately after the

rising edge of the ACK bit. This applies to each transferred byte, independently of whether this is a byte-write or

a block-write sequence.

If the EEPROM write cycle is initiated, the data of the internal SMBus register is written into the EEPROM.

During EEPROM write, no data is allowed to be sent to the device via the SMBus until the programming

sequence is completed. Data, however, can be read out during the programming sequence (byte read or block

read). The programming status can be monitored by EEPIP, byte 24 bit 7.

The offset of the indexed byte is encoded in the command code, as described in Table 1.

The block-write and block-read protocol is outlined in Figure 9 and Figure 10, whereas Figure 7 and Figure 8

outline the corresponding byte-write and byte-read protocol.

A6

A5

A4

A3

A2

A1(1)

A0(1)

R/W

1

1

0

1

0

0

1

0

(1) Address bits A0 and A1 are programmable by the configuration inputs S0 and S1 (byte 10 bits [1:0] and bits [3:2]. This allows

addressing up to four devices connected to the same SMBus.

Table 1. Command Code Definition

Bits

Description

7

0 = Block-read or block-write operation

1 = Byte-read or byte-write operation

6–0

Byte offset for read and write operations

12

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