7.2.2.4 Designing the Bootstrap Supply

The bootstrap capacitor (C2, Figure 7-1) is charged during the PWM on-time of the low-side FET of the

left-hand-side half bridge. During the PWM off-time, C2 rises with the switch pin voltage and serves as the

AMC0106M25 power supply. R4 serves as a current-limiting resistor during the charging phase, and D1 prevents

reverse current from flowing back to the bootstrap supply during the discharge phase.

The voltage C2 charges up to during the PWM on-time depends on the values of the bootstrap supply and the

current limiting resistor R2. Additionally, this voltage depends on the PWM duty cycle and the forward voltage of

the diode D1 (VF, D1).

The voltage C2 discharges to during the PWM off-time depends on the reverse recovery time of D1. Additionally,

this voltage depends on the PWM duty cycle and the current draw of the AMC0106M25 (IAVDD) . To minimize

switching losses, select a fast switching diode with high forward current capability.

Make sure C2 is sized to support the maximum IAVDD current for the duration of the maximum PWM off-time.

During this time, make sure C2 does not discharge below the minimum recommended AVDD voltage of 3V.

Lower capacitance values allow faster charging and therefore support lower PWM duty cycles. However, lower

values also generate more voltage ripple and limit the maximum PWM off time. In this example, a ripple voltage

(VRIPPLE) of less than 200mV is targeted. The maximum PWM off-time is 95% × (1 / fPWM) = 0.95 × 62.5µs,

which is approximately 60µs. IAVDD, MAX is specified as 8.8mA. The minimum capacitance value is calculated as

C2, MIN = IAVDD, MAX × tPWM-OFF, MAX / VRIPPLE = 8.8mA × 60µs / 200mV = 2.6µF. A 4.7µF capacitor is selected to

allow for component tolerances and adds margin to the design.

Make sure the bootstrap circuit supports recharging C2 within the minimum PWM on-time of 5% × (1 / fPWM)

= 0.05 × 62.5µs, or approximately 3.1µs. The average charging current during this time is C2 × VRIPPLE /

tPWM-ON, MIN = 4.7µF × 200mV / 3.1µs, which is approximately 300mA. This current is the minimum forward

current that diode D1 has to support. The maximum allowable voltage drop across diode D1 and current limiting

resistor R4 is determined by the minimum capacitor voltage and the VBS value. The minimum capacitor voltage

is 3V and equivalent to AVDDMIN. VBS is the bootstrap supply voltage and is equal to 6V. Assume a diode

forward voltage of 1V is used. Make sure R4 is < (VBS – VF, D1 – VC2, MIN ) / ICHARGE = (6V – 1V – 3V) / 300mA =

6Ω. A 2Ω resistor is selected to provide margin to the design.

7.3 Best Design Practices

Place a minimum 10nF capacitor at the device input (from INP to INN). This capacitor helps avoid voltage droop

at the input during the sampling period of the switched-capaitor input stage.

Do not leave the inputs of the AMC0106M25 unconnected (floating) when the device is powered up. If either

modulator input is left floating, the output bitstream is not valid.

Connect the high-side ground (AGND) to INN, either by a hard short or through a resistive path. A DC current

path between INN and AGND is required to define the input common-mode voltage. Do not exceed the input

common-mode range, as specified in the Recommended Operating Conditions table. For best accuracy, route

the ground connection as a separate trace that connects directly to the sense resistor. Do not short AGND to

INN directly at the device input. See the Layout section for more details.

AMC0106M25

SBASAX1 – AUGUST 2024

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