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100

95

90

85

80

75

70

65

60

Clock Duty Cycle

− %

35

40

50

45

55

65

60

SFDR

SNR

f

IN = 20MHz

95

90

85

80

75

70

65

60

Differential Clock Amplitude

− V

0

0.5

1.0

1.5

2.0

2.5

3.0

f

IN = 70MHz

SFDR

SNR

OUTPUT INFORMATION

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

Figure 46. AC Performance vs Clock Duty Cycle

Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When

using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using a

differential clock allows for the use of larger amplitudes without exceeding the supply rails and absolute

maximum ratings of the ADC clock input. Figure 47 shows the performance variation of the device versus input

clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see the

ADS55xxEVM User's Guide (SLWU010), available for download from www.ti.com.

Figure 47. AC Performance vs Clock Amplitude

The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal

(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals one when the output reaches the

full-scale limits.

Two different output formats (straight offset binary or two's complement) and two different output clock polarities

(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one

of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active

high) is provided to put the outputs into a high-impedance state.

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