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DAC8580IPWR bảng dữ liệu(PDF) 12 Page - Texas Instruments |
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DAC8580IPWR bảng dữ liệu(HTML) 12 Page - Texas Instruments |
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12 / 26 page ![]() www.ti.com THEORY OF OPERATION LPF DAC8580 − + Output Driver De-glitcher − + I-to-V Converter Iout DAC @ Output Voltage (VOUT) DAC8580 SLAS458B – JUNE 2005 – REVISED AUGUST 2005 The traditional high-speed, voltage-output D/A conversion employs a current-output DAC followed by an I-to-V conversion amplifier. For voltage waveform generation applications, these components are typically followed by a sample-and-hold de-glitcher circuit, an analog low-pass filter, and an external buffer to drive low-impedance loads (see Figure 33). Monolithic applications of such traditional architectures suffer from the imperfections of on-chip sample-and-hold circuits, and the analog filters. Multi-chip applications of this traditional architecture suffer from voltage drift problems due to the temperature coefficient mismatches between external passive components and the D/A converter, as well as large circuit size and high cost. DAC8580 is designed to address the problems of traditional high-speed, high-resolution, voltage-output D/A converters. Figure 33. Traditional Voltage Output Waveform Generation Circuitry Replaced by a Single DAC8580 The DAC8580 uses a proprietary, inherently monotonic, high-speed, low-glitch, resistor-string architecture, followed by an on-chip low-noise output amplifier. 16-bit input data is coded in twos-complement format and transmitted using a 3-wire serial interface (MSB first). The input data is sent to an on-chip digital interpolation filter. The filter can be programmed to different oversampling rates, it can be bypassed, or it can be totally disabled. The digital data is then decoded to select a tap voltage of the resistor string. The resistor-string output is sent to a high-speed, low-noise output amplifier. The output buffer has quasi-rail-to-rail swing capability (within 250-mV range of each rail) on a 600- Ω, 200-pF load. Loads of 50 Ω or 75 Ω can also be continuously driven as long as the output current remains within ±25 mA. The DAC8580 reduces the components that are used for implementing sample-and-hold circuits, analog filters, and output driver amplifiers. The resistor-string DAC architecture provides low glitch, exceptional differential linearity, and temperature stability while the output buffer provides fast settling and exceptionally low noise (20 nV/ √Hz). The DAC8580 settles well under 1 µs for large signals. The small-signal settling time is less than 150 ns, which enables (oversampled) update rates exceeding 6.7 MSPS. If some small-signal settling error can be tolerated, the DAC8580 can update as fast as 16 MSPS. Due to the remarkably low glitch energy, the DAC8580 has low harmonic distortion ( –70 dB THD for 1-kHz sine wave output). When the linearity error of the DAC8580 is calibrated using a lookup table, the THD performance typically exceeds 98 dBs, without an external S/H circuit. The DAC8580 needs a low-noise external reference voltage to set its output voltage range. The DAC8580 does not introduce glitches to the external voltage source. This significantly reduces the crosstalk when a single external reference is used to supply the reference voltage for multiple devices. The DAC8580 has a 3-wire serial interface to communicate with a microprocessor or a DSP. The host is not overloaded by the DAC8580: When the digital filter is on, the host needs only to send 1-out-of-16 data points (for oversampling rate 16). The digital filter of the DAC8580 can generate the remaining data points digitally, on-chip. When the digital filter is disabled (bypassed), the DAC8580 operates as a standard, 16-bit, 2-MSPS, voltage-output DAC. The 1.8-V to 5.5-V digital interface of the DAC8580 enables compatibility with various logic families. The DAC8580 uses a high-performance rail-to-rail output buffer capable of driving a 600- Ω, 200-pF load with fast 1-µs large-signal settling. The buffer has exceptional noise performance (20 nV/ √Hz) and fast slew-rate (35 V/µs). The small-signal settling time is under 150 ns, supporting DAC update rates exceeding 6.7 MSPS. 12 Not Recommended For New Designs |
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