DLPA2000 datasheet(16/58 Pages) TI2

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PROJ_ON

VBIAS

VOFS

VRST

VCORE

VLED

STATE

STANDBY

ACTIVE2

V2V5

LS_OUT (1.8 V)

INTZ

RESETZ

OFF

10 ms

25 ms

ACTIVE1

5 ms (min)

DMD_EN

in register 0x01h

” 10 ms

Startup DPP

System Power

(VINx)

10 ms

DMD

initialization

by DPP

•10 ms

Pad DMD_EN

by DPP through

SPI write

Stop Regulating

VBIAS

Stop Regulating

VRST

145 ms

DLPA2000

DLPS043B – JUNE 2014 – REVISED FEBRUARY 2018

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7.3 Feature Description

7.3.1 DMD Regulators

DLPA2000 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and

VRST. After pulling the PROJ_ON pin high, the DMD is first initialized followed by a power-up of the VOFS line

after a small delay of less than 10 ms followed by VBIAS and VRST with an additional delay of 145 ms. The LED

driver and STROBE DECODER circuit can only be enabled after all three rails are enabled. There are two

power-down sequences, the normal power-down timing initiated after pulling the PROJ_ON pin low, and a fast

power-down mode where if any one of the rails encounters a fault such as an output short, all three rails are

discharged simultaneously. The detailed power-up and power-down diagrams are shown in Figure 5 and

Figure 6.

Figure 5. Power Sequence Normal Shutdown Mode

NOTE

All values are typical (unless otherwise noted).

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