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THS6002IDWPR.A bảng dữ liệu(PDF) 32 Page - Texas Instruments |
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THS6002IDWPR.A bảng dữ liệu(HTML) 32 Page - Texas Instruments |
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32 / 47 page ![]() THS6002 DUAL DIFFERENTIAL LINE DRIVERS AND RECEIVERS SLOS202E− JANUARY 1998− REVISED MARCH 2007 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION PCB design considerations (continued) Additional 4 vias outside of thermal pad area but under the package Via diameter = 25 mils (0,635 mm)) Thermal pad area (150 mils x 170 mils) (3,81 mm x 4,32 mm) with 5 vias Via diameter = 13 mils(0,33 mm) Figure 57. PowerPad PCB Etch and Via Pattern The actual thermal performance achieved with the THS6002 in its PowerPAD package depends on the application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches (76,2 mm x 76,2 mm), then the expected thermal coefficient, θJA, is about 21.5_C/W. For a given θJA, the maximum power dissipation is shown in Figure 58 and is calculated by the following formula: P D + T MAX –T A q JA Where: PD = Maximum power dissipation of THS6002 (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature ( °C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case (0.37°C/W) θCA = Thermal coefficient from case to ambient More complete details of the PowerPAD installation process and thermal management techniques can be found in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering. |
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