3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum

output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load

measured in megaohms; much larger than the minimum calculated above.

4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase

can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd

Calculation.

9.2.3 Application Curve

QA

QB

SER

QC

QD

QE

QF

QG

QH

QH¶

SRCLK rising edge shifts data

in the serial registers only

QA

QB

SER

QC

QD

QE

QF

QG

QH

QH¶

RCLK rising edge shifts data

to the output registers

Figure 9-2. Simplified functional diagram showing clock operation

SN74HCS596

SCLS840 – AUGUST 2020

www.ti.com

16

Submit Document Feedback

Copyright © 2020 Texas Instruments Incorporated

Product Folder Links: SN74HCS596