OUTPUT

VOLTAGE

SHUTDOWN

PULSE

(2V/div)

17

LMV712-N, LMV712-N-Q1

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SNOS534J – FEBRUARY 2001 – REVISED NOVEMBER 2016

Product Folder Links: LMV712-N LMV712-N-Q1

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Copyright © 2001–2016, Texas Instruments Incorporated

Feature Description (continued)

The output stage is composed of a PMOS and a NPN transistor in a common source or emitter configuration,

delivering a rail-to-rail output excursion.

The MN4 transistor ensures that the LMV712-N output remains near V− when the amplifier is in shutdown mode.

7.4 Device Functional Modes

7.4.1 Shutdown Pin

The LMV712-N offers independent shutdown pins for the dual amplifiers. When the shutdown pin is tied low, the

respective amplifier shuts down and the supply current is reduced to less than 1 µA. In shutdown mode, the

output level of the amplifier stays at V−. In a 2.7-V operation, when a voltage from 1.5 V to 2.7 V is applied to the

shutdown pin, the amplifier is enabled. As the amplifier is coming out of the shutdown mode, the output

waveform ramps up without any glitch.

Figure 31. Output Recovery from Shutdown

A glitch-free output waveform is highly desirable in many applications, one of which is power amplifier control

loops. In this application, the LMV712-N is used to drive the power amplifier's power control. If the LMV712-N did

not have a smooth output ramp during turn on, it would directly cause the power amplifier to produce a glitch at

its output. This adversely affects the performance of the system.

To enable the amplifier, the shutdown pin must be pulled high. It must not be left floating in the event that any

leakage current may inadvertently turn off the amplifier.

7.4.2 Capacitive Load Tolerance

The LMV712-N can directly drive 200 pF in unity-gain without oscillation. The unity-gain follower is the most

sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers.

The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in

either an underdamped pulse response or oscillation. To drive a heavier capacitive load, TI recommends the

circuit in Figure 32.