ack from slave

ack from slave

w

rs

r

stop

ack from slave

ack from master

repeated start

data from slave

start

w ack

ack

rs

r ack

ack stop

start

SCL

SDA

MSB Chip Address LSB

slave address = 1100000

register address = 0x00h

MSB Register 0x00h LSB

MSB

Data

LSB

MSB Chip Address LSB

slave address = 1100000

register 0x00h data

ack

ack

ack

ack

START

MSB

DEVICE ADDRESS

LSB

ACK

SCL

SDA

STOP

MSB

REGISTER DATA

LSB

ACK

R/W

LM48824

www.ti.com

SNAS479D – MARCH 2009 – REVISED MAY 2013

Figure 31. I2C Write Cycle

Figure 32. Example I2C Read Cycle

Table 1. Device Address

B7

B6

B5

B4

B3

B2

B1

B0 (R/W)

Device

1

1

0

0

0

0

0

X

Address

Table 2. I2C Control Registers(1)

Register

Register

B7

B6

B5

B4

B3

B2

B1

B0

Address

Name

MODE

0x01h

HPL_EN

HPR_EN

0

0

0

0

THRM

SHDN

CONTROL

VOLUME

0x02h

MUTE_L

MUTE_R

VOL4

VOL3

VOL2

VOL1

VOL0

0

CONTROL

OUTPUT

0x03h

0

0

0

0

LOW_THD

0

HiZ_L

HiZ_R

CONTROL

DEVICE

0x04h

INFORMATIO

0

1

0

0

0

0

0

0

N (Read-Only)

(1)

All registers default to 0 on initial power-up except SHDN, MUTE_L, MUTE_R bits default to 1 at power-up.

Table 3. Mode Control Register

Bit

Name

Value

Description

0

Device enabled

B0

SHDN

1

Device disabled

0

Thermal-protection inactive

THRM

B1

(Read Only)

1

Thermal-protection active

0

Right channel amplifier disabled

B6

HPR_EN

1

Right channel amplifier enabled

0

Left channel amplifier disabled

B7

HPL_EN

1

Left channel amplifier enabled

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