USB3300 datasheet(35/55 Pages) SMSC

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Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

SMSC USB3300

Revision 1.08 (11-07-07)

DATASHEET

While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and

the Vbus voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6.6, "Interface Signal

Mapping During Low Power Mode". Linestate[1:0] is the combinational output of the full speed

receivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When an

unmasked interrupt or linestate change has occurred, the Link is notified and can determine if it should

wake-up the PHY.

An unmasked interrupt can be caused by the following comparators changing state, VbusVld, SessVld,

SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and either their

rising or falling edge interrupt is enabled, DATA[3] will assert. During Low Power Mode, the VbusVld

and SessEnd comparators can have their interrupts masked to lower the suspend current. Refer to

Section 6.1.9.4, "Minimizing Current in Low Power Mode".

While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are

stopped during Low Power Mode.

Figure 6.8 Entering Low Power Mode

Table 6.6 Interface Signal Mapping During Low Power Mode

SIGNAL

MAPS TO

DIRECTION

DESCRIPTION

linestate[0]

DATA[0]

OUT

Combinatorial linestate[0] driven directly by FS analog receiver.

linestate[1]

DATA[1]

OUT

Combinatorial linestate[1] driven directly by FS analog receiver.

reserved

DATA[2]

OUT

Driven Low

int

DATA[3]

OUT

Active high interrupt indication. Must be asserted whenever any

unmasked interrupt occurs.

reserved

DATA[7:4]

OUT

Driven Low

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(reg write)

Idle

Reg Data[n]

Idle

T10

Turn

Around

Low Power Mode

SUSPENDM

(ULPI Register Bit)

...

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