TLV5619EP

2.7 V TO 5.5 V 12BIT PARALLEL DIGITALTOANALOG CONVERTER

WITH POWER DOWN

SGLS124A − JULY 2002 − REVISED DECEMBER 2003

13

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

parallel interface

The device latches data on the positive edge of WE. It must be enabled with CS low. LDAC low updates the

DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update

is not necessary. However, to control the DAC using the load feature, LDAC can be driven low after the positive

WE edge.

Address

Decoder

A(0−15)

IS

WE

D(0−15)

CS

LDAC

WE

D(0−11)

TMS320C2XX, 5X

TLV5619

Figure 11. Proposed Interface Between TLV5619 and TMS320C2XX, 5X DSPs

Address

Decoder

A(0−15)

TCLK0

R/W

D(0−15)

CS

LDAC

WE

D(0−11)

TMS320C3X

TLV5619

IOSTROBE

Figure 12. Proposed Interface Between TLV5619 and TMS320C3X DSPs