TLV2556

SLAS355B – DECEMBER 2001 – REVISED DECEMBER 2015

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6.9 Timing Requirements, VREF+ = 5 V

over recommended operating free-air temperature range,

VREF+ = 5 V, I/O CLOCK frequency = 15 MHz, VCC = 5 V, Load = 25 pF (unless otherwise noted)

MIN

MAX

UNIT

tw1

Pulse duration I/O CLOCK high or low

26.7

100000

ns

tsu1

Set-up time DATA IN valid before I/O CLOCK rising edge (see Figure 47)

12

ns

th1

Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 47)

0

ns

tsu2

Setup time CS low before first rising I/O CLOCK edge(1) (see Figure 48)

25

ns

th2

Hold time CS pulse duration high time (see Figure 48)

100

ns

th3

Hold time CS low after last I/O CLOCK falling edge (see Figure 48)

0

ns

th4

Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 49)

2

ns

th5

Hold time CS high after EOC rising edge when CS is toggled (see Figure 52)

0

ns

th6

Hold time CS high after INT falling edge (seeFigure 52)

0

ns

Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held low

th7

10

ns

(seeFigure 53)

Load = 25 pF

28

Delay time CS falling edge to DATA OUT valid (MSB or

td1

ns

LSB) (see Figure 46)

Load = 10 pF

20

td2

Delay time CS rising edge to DATA OUT high impedance (see Figure 46)

10

ns

td3

Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 49)

2

20

ns

td4

Delay time last I/O CLOCK falling edge to EOC falling edge (seeFigure 50)

55

ns

td5

Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion

1.5

μs

td6

Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 50)

tconvert(max)

ns

Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB 1st

td7

4

ns

(see Figure 51)

td9

Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 53)

1

28

ns

tt1

Transition time I/O CLOCK(1) (see Figure 49)

1

μs

tt2

Transition time DATA OUT (see Figure 49)

5

ns

tt3

Transition time INT/EOC, CL = 7 pF (see Figure 50 and Figure 51)

2.4

ns

tt4

Transition time DATA IN, CS

10

μs

tcycle

Total cycle time (sample, conversion and delays)(1)

See (2)

μs

Source impedance = 25

Ω

600

Source impedance = 100

Ω

650

Channel acquisition time (sample) at 1 k

Ω(1)

tsample

ns

(see Figure 1 through Figure 6)

Source impedance = 500

Ω

700

Source impedance = 1 k

Ω

1000

(1)

I/O CLOCK period = 8 × [1/(I/O CLOCK frequency)] or 12 × [1/(I/O CLOCK frequency)] or 16 × [1/(I/O CLOCK frequency)], depending

on I/O format selected

(2)

tconvert(max) + I/O CLOCK period (8/12/16 CLKs)

(1)

8

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