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TLK1221 bảng dữ liệu(PDF) 5 Page - Texas Instruments

tên linh kiện TLK1221
Giải thích chi tiết về linh kiện  ETHERNET TRANSCEIVER
PDF  21 Pages
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nhà sản xuất  TI2 [Texas Instruments]
Trang chủ  https://www.ti.com
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TLK1221 bảng dữ liệu(HTML) 5 Page - Texas Instruments

  TLK1221 Datasheet HTML 1Page - Texas Instruments TLK1221 Datasheet HTML 2Page - Texas Instruments TLK1221 Datasheet HTML 3Page - Texas Instruments TLK1221 Datasheet HTML 4Page - Texas Instruments TLK1221 Datasheet HTML 5Page - Texas Instruments TLK1221 Datasheet HTML 6Page - Texas Instruments TLK1221 Datasheet HTML 7Page - Texas Instruments TLK1221 Datasheet HTML 8Page - Texas Instruments TLK1221 Datasheet HTML 9Page - Texas Instruments Next Button
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DXX.X
K28.5
DXX.X
DXX.X
K28.5
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
DXX.X
K28.5
K28.5
DXX.X
DXX.X
31Bit
Times
MaxReceive
PathLatency
WorstCase
MisalignedK28.5
MisalignmentCorrected
INPUTDATA
RBC0
RBC1
RD(0–9)
SYNC
CorruptData
30Bit
Times(Max)
TLK1221
www.ti.com....................................................................................................................................... SLLS713C – FEBRUARY 2007 – REVISED SEPTEMBER 2009
Comma Character on Expected Boundary
These devices provide 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial
input data to the 7-bit synchronization pattern. The K28.5 character is defined by the 8b/10b coding scheme as a
pattern consisting of 0011 1110 10 (a negative number beginning with disparity), with the 7 MSBs (0011 111)
referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.
As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly
aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1, SYNC
and RD0–RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1).
Comma Character Not on Expected Boundary
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the
misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 4. The
RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design,
the maximum stretch that occurs is 20 bit times. This occurs during a worst-case scenario when the K28.5 is
aligned to the falling edge of RBC1 instead of the rising edge. Figure 4 shows the timing characteristics of the
data realignment.
Figure 4. Word Realignment Timing Characteristic Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data.
Data Reception Latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as the first bit. The minimum latency in TBI mode is 18 bit times and the
maximum latency is 24 bit times.
Copyright © 2007–2009, Texas Instruments Incorporated
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