TIBPAL16R4-10C, TIBPAL16R6-10C, TIBPAL16R8-10C

HIGH-PERFORMANCE

IMPACT-X ™ PAL® CIRCUITS

SRPS017 − D3023, MAY 1987 − REVISED DECEMBER 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

16

metastable characteristics of TIBPAL16R4-10C, TIBPAL16R6-10C, and TIBPAL16R8-10C

At some point a system designer is faced with the problem of synchronizing two digital signals operating at two

different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock

through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time

specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop

can influence overall system reliability.

Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said

to be in the metastable state if the output hangs up in the region between VIL and VIH. This metastable condition

lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum

propagation delay time (CLK to Q max).

From a system engineering standpoint, a designer cannot use the specified data sheet maximum for

propagation delay time when using the flip-flop as a data synchronizer − how long to wait after the specified data

sheet maximum must be known before using the data in order to guarantee reliable system operation.

The circuit shown in Figure 4 can be used to evaluate MTBF (Mean Time Between Failure) and Δt for a selected

flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.

When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.

The outputs of the two comparators are sampled a selected time (Δt) after SCLK. The exclusive OR gate detects

the occurrence of a failure and increments the failure counter.

C1

C1

+

1D

1D

C1

C1

1D

VIH

Comparator

VIL

Comparator

Noise

Generator

DUT

MTBF

Counter

1D

DATA IN

SCLK

SCLK + Δt

Figure 4. Metastable Evaluation Test Circuit

In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied

so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 5.

Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.

Δt

Δt

SCLK + Δt

trec = Δt − CLK to Q (max)

MTBF +

Time (sec)

# Failures

Data

SCLK

Figure 5. Timing Diagram

TIBPAL16R4-10C, 'R6-10C, 'R6-12M, 'L8-12M are Not Recommended for New Designs. TIBPAL16R8-10C, 'R8-12M are Obsolete.