tw(H)

tw(L)

tr

tf

tsu(1)

th(1)

SCL

SDA

tsu(2)

th(2)

tsu(3)

t(buf)

SCL

SDA

StartCondition

StopCondition

THS7347

www.ti.com

SLOS531B

– MAY 2007 – REVISED OCTOBER 2011

TIMING REQUIREMENTS FOR I

2C INTERFACE(1)(2)

At VDD = 2.7 V to 5 V.

STANDARD MODE

FAST MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

fSCL

Clock frequency, SCL

0

100

0

400

kHz

tw(H)

Pulse duration, SCL high

4

0.6

μs

tw(L)

Pulse duration, SCL low

4.7

1.3

μs

tr

Rise time, SCL and SDA

1000

300

ns

tf

Fall time, SCL and SDA

300

300

ns

tsu(1)

Setup time, SDA to SCL

250

100

ns

th(1)

Hold time, SCL to SDA

0

0

ns

t(buf)

Bus free time between stop and start conditions

4.7

1.3

μs

tsu(2)

Setup time, SCL to start condition

4.7

0.6

μs

th(2)

Hold time, start condition to SCL

4

0.6

μs

tsu(3)

Setup time, SCL to stop condition

4

0.6

μs

Cb

Capacitive load for each bus line

400

400

pF

(1)

The THS7347 I2C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.

(2)

The THS7347 was designed to comply with version 2.1 of the I2C specification.

Figure 1. SCL and SDA Timing

Figure 2. Start and Stop Conditions

Copyright

© 2007–2011, Texas Instruments Incorporated

9