TFP403

TI

PanelBus™ DIGITAL RECEIVER

SLDS125B − DECEMBER 2000 − REVISED MAY 2011

11

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

detailed description

fundamental operation

The TFP403 is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel

display systems to receive and decode TMDS encoded RGB pixel data streams. In a digital display system a

host, usually a PC or workstation, contains a DVI compatible transmitter that receives 24 bit pixel data along

with appropriate control signals. The transmitter encodes them into a high-speed low-voltage differential serial

bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually

a flat-panel monitor, will require a DVI compatible receiver like the TI TFP403 to decode the serial bit stream

back to the same 24 bit pixel data and control signals that originated at the host. This decoded data can then

be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display

can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To

support modern display resolutions up to UXGA a high bandwidth receiver with good jitter and skew tolerance

is required.

TMDS pixel data and control signal encoding

TMDS stands for transition minimized differential signaling. Only one of two possible TMDS characters for a

given pixel will be transmitted at a given time. The transmitter keeps a running count of the number of ones and

zeros previously sent and transmits the character that will minimize the number of transitions and approximate

a dc balance of the transmission line.

Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three

channels also receive control signals, HSYNC, VSYNC, and user defined control signals CTL[2:1]. These

control signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The

following table maps the received input data to appropriate TMDS input channel in a DVI compliant system.

RECEIVED PIXEL DATA

ACTIVE DISPLAY DE = HIGH

INPUT CHANNEL

OUTPUT PINS

(VALID FOR DE = HIGH)

Red[7:0]

Channel – 2 (Rx2 ±)

QE[23:16] QO[23:16]

Green[7:0]

Channel – 1 (Rx1 ±)

QE[15:8] QO[15:8]

Blue[7:0]

Channel – 0 (Rx0 ±)

QE[7:0] QO[7:0]

RECEIVED CONTROL DATA

BLANKING DE = LOW

INPUT CHANNEL

OUTPUT PINS

(VALID FOR DE = LOW)

CTL[3:2] (see Note 7)

Channel – 2 (Rx2 ±)

CTL2

CTL[1: 0] (see Note 7)

Channel – 1 (Rx1 ±)

CTL1

HSYNC, VSYNC

Channel – 0 (Rx0 ±)

HSYNC, VSYNC

NOTE 7: Some TMDS transmitters transmit a CTL0 signal. The TFP403 decodes and

transfers CTL[2:1] and ignores CTL0 characters. CTL3 is used internally to enable

HDCP decryption. CTL3 and CTL0 are not available as TFP501 outputs.

The TFP403 discriminates between valid pixel TMDS characters and control TMDS characters to determine

the state of active display versus blanking, i.e., state of DE.