±1

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

10

Time (ns)

VIN

VOUT

C001

SN74LVC2G04

SCES195N – APRIL 1999 – REVISED AUGUST 2015

www.ti.com

Typical Application (continued)

9.2.3 Application Curve

There is a slight delay from input to output in addition to the voltage change. Figure 4 shows the expected output

of the SN74LVC2G04 when an input is switched from 0 to 5 V and VCC is set at 1.8 V. With VCC set to 1.8 V, the

output switches at 1.17 V (0.65 × VCC), and therefore the input can be anything from 1.18 V up to 6.5 V and the

SN74LVC2G04 will work perfectly.

Figure 4. Simulated Voltage Down-Translation from 5-V Input to 1.8-V Output With tpd = 3.4 ns.

10 Power Supply Recommendations

The power supply can be any voltage between the min and max supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply a 0.1-

μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF

capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different

frequencies of noise. 0.1-

μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be

installed as close to the power pin as possible for best results.

10

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