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AR0130CSSC00SPBA0-DP1 bảng dữ liệu(PDF) 10 Page - ON Semiconductor |
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AR0130CSSC00SPBA0-DP1 bảng dữ liệu(HTML) 10 Page - ON Semiconductor |
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10 / 40 page ![]() AR0130CS www.onsemi.com 10 OUTPUT DATA FORMAT The AR0130 image data is read out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking (see Figure 8). The amount of horizontal row time (in clocks) is programmable through R0x300C. The amount of vertical frame time (in rows) is programmable through R0x300A. LINE_VALID (LV) is HIGH during the shaded region of Figure 8. Optional Embedded Register setup information and Histogram statistic information are available in first 2 and last row of image data. Figure 8. Spatial Illustration of Image Readout P0,0 P0,1 P0,2 .....................................P 0,n−1 P0,n P1,0 P1,1 P1,2 .....................................P 1,n−1 P1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 Pm−1,0 Pm−1,1 .....................................P m−1,n−1 Pm−1,n Pm,0 Pm,1 .....................................P m,n−1 Pm,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 VALID IMAGE HORIZONTAL BLANKING VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING Readout Sequence Typically, the readout window is set to a region including only active pixels. The user has the option of reading out dark regions of the array, but if this is done, consideration must be given to how the sensor reads the dark regions for its own purposes. Parallel Output Data Timing The output images are divided into frames, which are further divided into lines. By default, the sensor produces 968 rows of 1288 columns each. The FV and LV signals indicate the boundaries between frames and lines, respectively. PIXCLK can be used as a clock to latch the data. For each PIXCLK cycle, with respect to the falling edge, one 12−bit pixel datum outputs on the DOUT pins. When both FV and LV are asserted, the pixel is valid. PIXCLK cycles that occur when FV is de−asserted are called vertical blanking. PIXCLK cycles that occur when only LV is de−asserted are called horizontal blanking. Figure 9. Default Pixel Output Timing |
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