3.3V

XSMT

I

2

S Clocks

SCK, BCK, LRCK

150t + 0.2ms

S

VDD

0V

High

Low

High

Low

Time

PCM5100, PCM5101, PCM5102

SLAS764B – MAY 2011 – REVISED SEPTEMBER 2012

www.ti.com

Recommended Powerdown Sequence

With inadequate system design, the PCM510x can exhibit some pop on power down. Pops are caused by the

device not having enough time to detect power loss and start the muting process.

The PCM510x evaluation board avoids audible pop with an electrolytic decoupling capacitor. This capacitor

provides enough time between data loss from USB or S/PDIF and power supply loss for the muting process to

take place.

The PCM510x has two auto-mute functions to mute the device upon power loss (intentional or unintentional).

XSMT = 0

When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog

mute. This process takes 150 sample times (ts) + 0.2mS.

As this mute time is mainly dominated by the sampling frequency, systems sampling at 192kHz will mute much

faster than a 48kHz system.

Clock Error Detect

When clock error is detected on the incoming data clock, the PCM510x family switches to an internal oscillator,

and continues to the drive the DAC, while attenuating the data from the last known value. Once this process is

complete, the PCM510x outputs will be hard muted to ground.

Planned Shutdown

These auto-muting processes can be manipulated by system designs to mute before power loss in the following

ways:

1. Assert XSMT low 150tS + 0.2mS before power is removed.

24

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