LP5523 datasheet(7/61 Pages) TI2

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LP5523

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SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

Product Folder Links: LP5523

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(1)

The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

Minimum and maximum limits are ensured by design, test, or statistical analysis.

(4)

Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics.

(5)

The I2C host must allow at least 500 µs before sending data to the LP5523 after the rising edge of the enable line.

6.9 Logic Interface Characteristics

Unless otherwise noted: typical limits are for TA = 25°C; minimum and maximum limits apply over the operating ambient

temperature range (

−30°C < TA < +85°C).See

(1) (2) (3) (4)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOGIC INPUT EN

VIL

Input low level

0.5

VIH

Input high level

1.2

Input current

−1

µA

tDELAY

Input delay(5)

µs

LOGIC INPUT SCL, SDA, TRIG, CLK, ASEL0, ASEL1

VIL

Input low level

0.2 × VEN

VIH

Input high level

0.8 × VEN

Input current

−1

µA

LOGIC OUTPUT SDA, TRIG, INT

VOL

Output low level

IOUT = 3 mA (pullup current)

0.3

0.5

Output leakage current

VOUT = 2.8 V

µA

LOGIC OUTPUT GPO

VOL

Output low level

IOUT = 3 mA

0.3

0.5

VOH

Output high level

IOUT = −2 mA

VDD − 0.5

VDD − 0.3

Output leakage current

VOUT = 2.8 V

µA

(1)

The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

Minimum and maximum limits are ensured by design, test, or statistical analysis.

(4)

Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD.

(5)

The ideal external clock signal for the LP5523 is a 0 V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz,

program execution is faster, and at frequencies below 32.7 kHz program execution is slower.

6.10 Recommended External Clock Source Conditions

Unless otherwise noted limits apply for TA = 25°C. See

(1) (2) (3) (4) (5)

MIN

NOM

MAX

UNIT

LOGIC INPUT CLK

ƒCLK

Clock frequency

32.7

kHz

tCLKH

High time

µs

tCLKL

Low time

µs

Clock rise time, 10% to 90%

µs

Clock fall time, 90% to 10%

µs

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