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ADC08D500 bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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ADC08D500 bảng dữ liệu(HTML) 5 Page - Texas Instruments |
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5 / 33 page ![]() LMH6523 www.ti.com SNOSC88 – DECEMBER 2012 ELECTRICAL CHARACTERISTICS - 5V (continued) The following specifications apply for single supply with V+ = 5V, Maximum Gain (0 Attenuation), RL = 200Ω, VOUT = 4VPPD, fin = 200 MHz, High Power Mode, Boldface limits apply at temperature extremes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE PINS VIL Logic Input Low Voltage Amplifier disabled 0 0.4 V VIM Logic Input Mid Level Amplifier Low Power Mode 0.6 1.9 V VIH Logic Input High Level Amplifier High Power Mode 2.2 5 V VSB Enable Pin Self Bias Voltage No external load 1.37 V IIL Input Bias Current, Logic Low Digital input voltage = 0.2V –200 µA IIM Input Bias Current, Logic Mid Digital input voltage = 1.5V 28 µA IIH Input Bias Current, Logic High Digital input voltage = 3.0V 500 µA PARALLEL MODE TIMING tGS Setup Time 3 ns tGH Hold Time 3 ns SERIAL MODE fCLK SPI Clock Frequency 50% duty cycle, ATE tested at 20MHz 20 50 MHz LOW POWER MODE (Enable pins are self biased) ICC Total Supply Current all four channels in low power mode 370 398 mA IBIAS Output Pin Bias Current External Inductor, No Load, VOUT<200mV 26 mA ICC Disabled Supply Current Enable Pin < 0.4V 74 mA Output Intermodulation Intercept OIP3 f = 200 MHz, VOUT = 4 dBm per tone 44 dBm Point P1dB 1dB Compression Point 16 dBm f = 100 MHz, VOUT =2 VPPD −90 dBc HD2 Second Order Harmonic Distortion f = 200 MHz, VOUT = 2 VPPD −79 dBc f = 100 MHz, VOUT = 2 VPPD −91 dBc HD3 Third Order Harmonic Distortion f = 200 MHz, VOUT = 2 VPPD −79 dBc Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LMH6523 |
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