LMC6772

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SNOS749F – SEPTEMBER 1995 – REVISED MARCH 2013

2.7V Electrical Characteristics

Unless otherwise specified, all limits ensured for TJ = 25°C, V

+ = 2.7V, V− = 0V, V

CM = V

+/2. Boldface limits apply at the

temperature extremes.

Symbol

Parameter

Conditions

Typ(1)

LMC6772AI LMC6772BI

LMC6772Q

Units

Limit(2)

Limit(2)

Limit(2)

VOS

Input Offset Voltage

3

5

15

10

mV

8

18

13

max

TCVOS

Input Offset Voltage Temperature

2.0

μV/°C

Drift

Input Offset Voltage Average

See(3)

3.3

μV/Mont

Drift

h

IB

Input Current

0.02

pA

IOS

Input Offset Current

0.01

pA

CMRR

Common Mode Rejection Ratio

75

dB

PSRR

Power Supply Rejection Ratio

±1.35V < VS < ±7.5V

80

dB

AV

Voltage Gain

(By Design)

100

dB

VCM

Input Common-Mode Voltage

CMRR > 55 dB

3.0

2.9

2.9

2.9

V

Range

2.7

2.7

2.7

min

−0.3

−0.2

−0.2

−0.2

V

0.0

0.0

0.2

max

VOL

Output Voltage Low

ILOAD = 2.5 mA

0.2

0.3

0.3

0.3

V

0.4

0.4

0.45

max

IS

Supply Current

For Both Comparators

12

20

20

20

μA

(Output Low)

25

25

25

max

ILeakage

Output Leakage Current

VIN(+) = 0.5V,

0.1

500

500

500

nA

VIN(−) = 0V, VO = 15V

1000

(1)

Typical Values represent the most likely parametric norm.

(2)

All limits are specified by testing or statistical analysis.

(3)

Input offset voltage Average Drift is calculated by dividing the accelerated operating life drift average by the equivalent operational time.

The input offset voltage average drift represents the input offset voltage change at worst-case input conditions.

Copyright © 1995–2013, Texas Instruments Incorporated

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