VAC-RMS-PK 2

VAC

t

VPEAK

LM3444

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SNVS682D – NOVEMBER 2010 – REVISED DECEMBER 2015

Application Information (continued)

From Figure 17 and the equation for current in a capacitor, i = C × dV/dt, the amount of capacitance needed at

VBUCK is calculated as follows.

At 60 Hz, and a valley-fill circuit of two stages, the hold-up time (tX) required at VBUCK is calculated as follows.

The total angle of an AC half cycle is 180° and the total time of a half AC line cycle is 8.33 ms. When the angle

of the AC waveform is at 30° and 150°, the voltage of the AC line is exactly ½ of its peak. With a two-stage

valley-fill circuit, this is the point where the LED string switches from power being derived from AC line to power

being derived from the hold up capacitors (C7 and C9). 60° out of 180° of the cycle or 1/3 of the cycle the power

is derived from the hold up capacitors (1/3 × 8.33 ms = 2.78 ms). This is equal to the hold up time (dt) from the

previous equation, and dv is the amount of voltage the circuit is allowed to droop. From Determining Maximum

Number of Series Connected LEDs Allowed, we know the minimum VBUCK voltage is about 45 V for a

90-VAC to 135-VAC line. At 90-VAC low-line operating condition input, ½ of the peak voltage is 64 V. Thus, with

some margin, the voltage at VBUCK can not droop more than about 15 V (dv). (i) is equal to (POUT/VBUCK), where

POUT is equal to (VLED × ILED). Total capacitance (C7 in parallel with C9) can now be calculated. See Typical

Application for further calculations of the valley-fill capacitors.

8.1.8 Determining Maximum Number of Series Connected LEDs Allowed

The LM3444 is an off-line buck topology LED driver. A buck converter topology requires that the input voltage

(VBUCK) of the output circuit must be greater than the voltage of the LED stack (VLED) for proper regulation. One

must determine what the minimum voltage observed by the buck converter is before the maximum number of

LEDs allowed can be determined. The following two variables must be determined to accomplish this:

1. AC line operating voltage. This is usually 90 VAC to 135 VAC for North America. Although the LM3444 can

operate at much lower and higher input voltages, a range is needed to illustrate the design process.

2. The number of stages implemented in the valley-fill circuit (1, 2, or 3).

In this example, the most common valley-fill circuit is used (two stages).

Figure 18. AC Line

Figure 18 shows the AC waveform. One can easily see that the peak voltage (VPEAK) is always given by

Equation 27.

(27)

The voltage at VBUCK with a valley-fill stage of two looks similar to the waveforms in Figure 17.

The purpose of the valley-fill circuit is to allow the buck converter to pull power directly off of the AC line when

the line voltage is greater than its peak voltage divided by two (two-stage valley-fill circuit). During this time, the

capacitors within the valley fill circuit (C7 and C8) are charged up to the peak of the AC line voltage. Once the

line drops below its peak divided by two, the two capacitors are placed in parallel and deliver power to the buck

converter. One can now see that if the peak of the AC line voltage is lowered due to variations in the line voltage,

the DC offset (VDC) lowers. VDC is the lowest value that voltage VBUCK encounters.

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