TAS3103ADBT datasheet(59/152 Pages) TI

59 / 152 page

2−25

8-Bit ALU Operation

(Without Saturation)

10110111

(−73)

−73

+ 11001101

(−51)

+ −51

10000100

(−124)

−124

+ 11010011

(−45)

+ −45

Rollover

01010111

(57)

−169

+ 00111011

(59)

10010010

(−110)

−110

Figure 2−20. DAP ALU Operation With Intermediate Overflow

The DAP processing clock is set by pins PLL0 and PLL1, with the source clock XTALI or MCLKI. The DAP operates

at speeds up to 136 MHz, which is sufficient to process 96-kHz audio.

2.5

Reset

The reset circuitry in the TAS3103A is shown in Figure 2−21. A reset is initiated by inputting logic 0 on the reset pin,

RST. A reset is also issued at power turnon by the internal 1.8-V regulator subsystem.

MCLKI

XTALI

DPLL

1.8-V Regulator Subsystem

Reset Timer

CLR

Lock

Chip Reset

VDDS

Enable

dpll_clk

PWR GOOD

RST

A_VDDS

Figure 2−21. TAS3103A Reset Circuitry

When the VDDS and A_VDDS voltage rise times from 0.1 V to 3.0 V are 5 ms or less, the internal 1.8-V regulator

subsystem holds the TAS3103A in reset at power on until regulation is reached. The duration of this signal permits

the TAS3103A to complete all power-on initialization without external control or circuitry.

When the VDDS and A_VDDS voltage rise times from 0.1 V to 3.0 V are greater than 5 ms, the TAS3103A must be

reset once VDDS and A_VDDS have reached a minimum of 3.0 V. This reset can be performed in one of two ways.

•

A valid RST can be applied by an external controller once VDDS and A_VDDS are at 3.0 volts or higher.

•

An external circuit can be employed to hold RST LOW until VDDS and A_VDDS are 3.0 volts or higher. An

RC circuit implementation of this is shown in Figure 2−22. The values for R and C should be chosen to

ensure that RST is held low until VDDS and A_VDDS have reached 3.0 volts or higher. The values of R and

C in this figure provide a delay of approximately 20 ms.

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