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CDC3RL02BYFPR bảng dữ liệu(PDF) 11 Page - Texas Instruments

tên linh kiện CDC3RL02BYFPR
Giải thích chi tiết về linh kiện  CDC3RL02 Low Phase-Noise Two-Channel Clock Fan-Out Buffer
PDF  23 Pages
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CDC3RL02BYFPR bảng dữ liệu(HTML) 11 Page - Texas Instruments

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source for optimum phase noise performance. The input range of the LDO allows the device to be powered
directly from a single cell Li battery. The LDO is enabled by either of the CLK_REQ_N signals. When disabled,
the device enters a low power shutdown mode consuming less than 1μA from the battery. The LDO requires
an output decoupling capacitor in the range of 1μF to 10μF with an equivalent series resistance (ESR) of at
least 0.1Ω for compensation and high-frequency PSR. This capacitor must stay within the specified range for
capacitance and ESR over the entire operating temperature range. A ceramic capacitor can be used if a small
external resistance is added in series with the capacitor to increase the effective ESR. An input bypass capacitor
of 1μF or larger is recommended.
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CDC3RL02
SCHS371H – NOVEMBER 2009 – REVISED OCTOBER 2024
Copyright © 2024 Texas Instruments Incorporated
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