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TUSB215-Q1

SLLSF07 – SEPTEMBER 2017

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Copyright © 2017, Texas Instruments Incorporated

Typical Application (continued)

8.2.1 Design Requirements

For this design example, use the parameters shown in the table below.

Table 3. Design Parameters

PARAMETER

VALUE

VCC (4.4 V to 5.5 V)

5 V

I2C support required in system (Yes/No)

No

AC Boost

REQ

Level

AC Boost Level 2:

REQ = 3.83 k

0-Ω

0

1.69 k ±1%

1

3.83 k ± 1%

2

DNI

3

DC Boost

RDC1

RDC2

Level

Mid DC Level:

RDC1 = DNI

RDC2 = DNI

22 kΩ - 47 kΩ

Do Not Install (DNI)

40 mV Low DC boost

DNI

DNI

60 mV Mid DC boost

47 kΩ

24 kΩ

80 mV High DC boost

8.2.2 Detailed Design Procedure

TUSB215-Q1 requires a valid reset signal as described in the power supply recommendations section. The

capacitor at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.

VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.

The ideal AC boost setting is dependent upon the signal chain loss characteristics of the target platform. The

general recommendation is to start with AC boost level 0, and then increment to AC boost level 1, etc. if

permissible. Same applies to the DC Boost setting where it is recommended to plan for the required pads or

connections to change boost settings, but to start with DC boost level 1.

In order for the TUSB215-Q1 to recognize any change to the AC and DC Boost settings, the RSTN pin must be

toggled. This is because the configuration is latched on power up and the inputs are ignored thereafter.

NOTE

The TUSB215-Q1 compensates for DC attenuation in the signal path according to the

configuration of the DC_BOOST pin. This pin is not 5V tolerant and therefore when

selecting the highest DC boost level, the voltage level at DC_BOOST pin must be less

than 3.6V.

Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.

Table 4. Platform Placement Guideline

PLATFORM GOAL

SUGGESTED DEVICE PLACEMENT

Pass USB Near End Mask

Close to measurement point

Pass USB Far End Eye Mask

Close to USB PHY

Cascade multiple devices to improve device enumeration

Midway between each USB interconnect