TSC2005 datasheet(6/46 Pages) TI2

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TIMING INFORMATION

BIT0

DIS(CSR-SDOZ)

H(SDI-SCLKR)

NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequireseightSCLKs.

H(SCLKF-SDOVALID)

SU(SDI-SCLKR)

D(CSF-SDOVALID)

SU(SCLKF-CSR)

WH(CS)

C(SCLK)

SU(CSF-SCLK1R)

WL(SCLK)

WH(SCLK)

BIT1

MSBIN

MSBOUT

CS SS

(

)

SCLK

SDO(MISO)

SDI(MOSI)

BIT0

BIT1

TIMING REQUIREMENTS

(1)

TSC2005

SBAS379C – DECEMBER 2006 – REVISED MARCH 2008

The TSC2005 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to

change output (MISO) data and the rising edge is used to latch input (MOSI) data. Eight SCLKs are required to

complete the Byte 1 command cycle, and 24 SCLKs are required for the Byte 0 command cycle. CS can stay low

during the entire 24 SCLKs of a Byte 0 command cycle, or multiple mixed cycles of reading and writing of bytes

and register accesses, as long as the corresponding addresses are supplied.

Figure 1. Detailed I/O Timing

All specifications typical at –40

°C to +85°C, SNSVDD = I/OVDD = 1.6V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tWL(RESET)

(2)

Reset low time

SNSVDD

≥ 1.6V

µs

SNSVDD = I/OVDD

≥ 1.6V and < 2.7V,

100

40% to 60% duty cycle

tC(SCLK)

SPI serial clock cycle time

SNSVDD = I/OVDD

≥ 2.7V and ≤ 3.6V,

40% to 60% duty cycle

SNSVDD = I/OVDD

≥ 1.6V and < 2.7V,

MHz

10pF load

fSCLK

SPI serial clock frequency

SNSVDD = I/OVDD

≥ 2.7V and ≤ 3.6V,

MHz

10pF load

tWH(SCLK)

SPI serial clock high time

0.4

× t

C(SCLK)

0.6

× t

C(SCLK)

tWL(SCLK)

SPI serial clock low time

0.4

× t

C(SCLK)

0.6

× t

C(SCLK)

tSU(CSF-SCLK1R)

Enable lead time

tD(CSF-SDOVALID)

Slave access time

tH(SCLKF-SDOVALID)

MISO data hold time

tWH(CS)

Sequential transfer delay

tSU(SDI-SCLKR)

MOSI data setup time

tH(SDI-SCLKR)

MOSI data hold time

tDIS(CSR-SDOZ)

Slave MISO disable time

tSU(SCLKF-CSR)

Enable lag time

Rise time

SNSVDD = I/OVDD = 3V, fSCLK = 25MHz

Fall time

SNSVDD = I/OVDD = 3V, fSCLK = 25MHz

(1)

All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2.

(2)

Refer to Figure 31.

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