Not Recommended for New Designs

TUSB8040

www.ti.com

SLLSE42I – SEPTEMBER 2010 – REVISED SEPTEMBER 2013

2.1

Clock and Reset Signals

Table 2-1. Clock and Reset Signals

SIGNAL NAME

TYPE

PIN NO.

DESCRIPTION

Global power reset. This reset brings all of the TUSB8040 internal registers to their default

GRSTz

I, PU

33

states. When GRSTz is asserted, the device is completely nonfunctional. GRSTz should

be asserted a minimum of 3 ms after all power rails are valid at the device.

Crystal input. This terminal is the crystal input for the internal oscillator. The input may

XI

I

76

alternately be driven by the output of an external oscillator. When using a crystal a 1-M

Ω

feedback resistor is required between XI and XO.

Crystal output. This terminal is crystal output for the internal oscillator. If XI is driven by an

XO

O

74

external oscillator this pin may be left unconnected. When using a crystal a 1-M

Ω feedback

resistor is required between XI and XO.

Oscillator return. If using a crystal, the load capacitors should use this signal as the return

VSSOSC

I

75

path and it should not be connected to the PCB ground. If using an oscillator, this terminal

should be connected to PCB Ground.

2.2

USB Upstream Signals

Table 2-2. USB Upstream Signals

SIGNAL NAME

TYPE

PIN NO.

DESCRIPTION

USB_SSTXP_UP

O

63

USB SuperSpeed transmitter differential pair (positive)

USB_SSTXM_UP

O

62

USB SuperSpeed transmitter differential pair (negative)

USB_SSRXP_UP

I

66

USB SuperSpeed receiver differential pair (positive)

USB_SSRXM_UP

I

65

USB SuperSpeed receiver differential pair (negative)

USB_DP_UP

I/O

70

USB high-speed differential transceiver (positive)

USB_DM_UP

I/O

69

USB high-speed differential transceiver (negative)

Precision resistor reference. A 9.09-K

Ω ±1% resistor should be connected between

USB_R1

PT

78

USB_R1 and USB_R1RTN.

USB_R1RTN

PT

79

Precision resistor reference return

USB Upstream port power monitor. The USB_VBUS input is a 1.2-V I/O cell and requires

a voltage divider to prevent damage to the input. The signal USB_VBUS must be

USB_VBUS

I

73

connected to VBUS through a 90.9-k

Ω ±1% resistor, and to signal ground through a 10-kΩ

±1% resistor. This allows the input to detect VBUS present from a minimum of 4 V and

sustain a maximum VBUS voltage up to 10 V (applied to the voltage divider).

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PIN DESCRIPTIONS

9

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