CD74HC08EP

QUADRUPLE 2INPUT POSITIVEAND GATES

SCLS477B − APRIL 2003 − REVISED APRIL 2004

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of Up

To −55

°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

D Buffered Inputs

D Typical Propagation Delay 7 ns

at VCC = 5 V, CL = 15 pF, TA = 25°C

D Fanout (Over Temperature Range)

− Standard Outputs ... 10 LSTTL Loads

− Bus Driver Outputs ... 15 LSTTL Loads

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Balanced Propagation Delay and Transition

Times

D Significant Power Reduction Compared to

LSTTL Logic ICs

D 2-V to 6-V VCC Operation

D High Noise Immunity NIL or NIH = 30% of

VCC at VCC = 5 V

D CMOS Input Compatibility, Il ≤ 1 µA at VOL,

VOH

description/ordering information

The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL

gates, with the low power consumption of standard CMOS integrated circuits. All devices can drive 10 LSTTL

loads.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − M

Tape and reel

CD74HC08QM96EP

HC08QEP

−55

°C to 125°C

SOIC − M

Tape and reel

CD74HC08MM96EP§

HC08MEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

§ Product Preview

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

H

L

XL

X

L

L

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

VCC

4B

4A

4Y

3B

3A

3Y

M PACKAGE

(TOP VIEW)

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.