CD74HC40103EP

HIGHSPEED CMOS LOGIC

8STAGE SYNCHRONOUS DOWN COUNTER

SCLS548 − DECEMBER 2003

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description/ordering information (continued)

If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a

counting sequence of 10016 or 25610 clock pulses long.

The CD74HC40103 may be cascaded using the TE input and the TC output in either synchronous or ripple

mode. These circuits have the low power consumption usually associated with CMOS circuitry, yet have speeds

comparable to low-power Schottky TTL circuits and can drive up to ten LSTTL loads.

FUNCTION TABLE†

CONTROL INPUTS

PRESET MODE

ACTION

MR

PL

PE

TE

PRESET MODE

ACTION

H

H

H

H

Inhibit counter

H

H

H

L

Synchronous

Count down

H

H

L

X

Synchronous

Preset on next positive clock transition

H

L

X

X

Asynchronous

Preset asynchronously

L

X

X

X

Asynchronous

Clear to maximum count

† See Figure 2 for timing diagram.

NOTE: H = high voltage level, L = low voltage level, X = don’t care

Clock connected to clock input

Synchronous operation: changes occur on negative-to-positive clock transitions.

Load inputs: MSB = P7, LSB = P0

logic diagram (positive logic)

7

10

11

12

13

4

5

6

P3

P4

P5

P6

P7

P0

P1

P2

15

9

3

1

2

16

8

14