AFE5803ZCF datasheet(24/53 Pages) TI2

24 / 53 page

AFE5803

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

www.ti.com

ADC Register Map

A reset process is required at the AFE5803 initialization stage. Initialization can be done in one of two ways:

1. Through a hardware reset, by applying a positive pulse at the RESET pin

2. Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high. Setting

this bit initializes the internal registers to the respective default values (all zeros) and then self-resets the

SOFTWARE RESET bit to low. In this case, the RESET pin can stay low (inactive).

After reset, all ADC and VCA registers are set to

‘0’, i.e. default settings. During register programming, all

reserved/unlisted register bits need to be set as

‘0’. Register settings are maintained when the AFE5803 is in

either partial power down mode or complete power down mode.

Table 2. ADC Register Map

ADDRESS

Default

FUNCTION

DESCRIPTION

(DEC)

(HEX)

Value

0[0]

0x0[0]

SOFTWARE_RESET

0: Normal operation;

1: Resets the device and self-clears the bit to '0'

0[1]

0x0[1]

REGISTER_READOUT_ENABLE

0:Disables readout;

1: enables readout of register at SDOUT Pin

1[0]

0x1[0]

ADC_COMPLETE_PDN

0: Normal

1: Complete Power down

1[1]

0x1[1]

LVDS_OUTPUT_DISABLE

0: Output Enabled;

1: Output disabled

1[9:2]

0x1[9:2]

ADC_PDN_CH

<7:0>

0: Normal operation;

1: Power down. Power down Individual ADC channels.

1[9]

→CH8…1[2]→CH1

1[10]

0x1[10]

PARTIAL_PDN

0: Normal Operation;

1: Partial Power Down ADC

1[11]

0x1[11]

LOW_FREQUENCY_

0: No suppression;

NOISE_SUPPRESSION

1: Suppression Enabled

1[13]

0x1[13]

EXT_REF

0: Internal Reference;

1: External Reference. VREF_IN is used. Both 3[15] and 1[13] should be set

as 1 in the external reference mode

1[14]

0x1[14]

LVDS_OUTPUT_RATE_2X

0: 1x rate;

1: 2x rate. Combines data from 2 channels on 1 LVDS pair. When ADC clock

rate is low, this feature can be used

1[15]

0x1[15]

SINGLE-ENDED_CLK_MODE

0: Differential clock input;

1: Single-ended clock input

2[2:0]

0x2[2:0]

RESERVED

Set to 0

2[10:3]

0x2[10:3]

POWER-DOWN_LVDS

0: Normal operation;

1: PDN Individual LVDS outputs. 2[10]

→CH8…2[3]→CH1

2[11]

0x2[11]

AVERAGING_ENABLE

0: No averaging;

1: Average 2 channels to increase SNR

2[12]

0x2[12]

LOW_LATENCY

0: Default Latency with digital features supported, 11 cycle latency

1: Low Latency with digital features bypassed, 8 cycle latency

2[15:13]

0x2[15:3]

TEST_PATTERN_MODES

000: Normal operation;

001: Sync;

010: De-skew;

011: Custom;

100:All 1's;

101: Toggle;

110: All 0's;

111: Ramp

3[7:0]

0x3[7:0]

INVERT_CHANNELS

0: No inverting;

1:Invert channel digital output. 3[7]

→CH8;3[0]→CH1

3[8]

0x3[8]

CHANNEL_OFFSET_

0: No offset subtraction;

SUBSTRACTION_ENABLE

1: Offset value Subtract Enabled

3[9:11]

0x3[9:11]

RESERVED

Set to 0

3[12]

0x3[12]

DIGITAL_GAIN_ENABLE

0: No digital gain;

1: Digital gain Enabled

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