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ADC14155QML-SP

SNAS378L – NOVEMBER 2008 – REVISED FEBRUARY 2019

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7.3.3.3 Clock Mode Select/Data Format (CLK_SEL/DF)

Single-ended versus differential clock mode and output data format are selectable using this quad-state function

pin. Table 4 shows how to select between the clock modes and the output data formats.

Table 4. Clock Mode And Data Format Selection Table

CLK_SEL/DF Input Voltage

Clock Mode

Output Data Format

VA

Differential

2's Complement

(2 / 3) * VA

Differential

Offset Binary

(1 / 3) * VA

Single-Ended

2's Complement

AGND

Single-Ended

Offset Binary

7.4 Device Functional Modes

This devices has no specific functional modes.