SAR

CONTROL

SERIAL

INTERFACE

COMPARATOR

S/H

CDAC

+IN

-IN

VREF

ADC121S705

SNAS355B – DECEMBER 2006 – REVISED MARCH 2013

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Block Diagram

PIN DESCRIPTIONS

Pin No.

Symbol

Description

Voltage Reference Input. A voltage reference between 1V and VA must be applied to this

input. VREF must be decoupled to GND with a minimum ceramic capacitor value of 0.1 µF.

1

VREF

A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended for

enhanced performance.

Non-Inverting Input. +IN is the positive analog input for the differential signal applied to the

2

+IN

ADC121S705.

Inverting Input.

−IN is the negative analog input for the differential signal applied to the

3

−IN

ADC121S705.

4

GND

Ground. GND is the ground reference point for all signals applied to the ADC121S705.

Chip Select Bar. CS is active low. The ADC121S705 is in Normal Mode when CS is LOW

5

CS

and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.

Serial Data Output. The conversion result is provided on DOUT. The serial data output word

6

DOUT

is comprised of 4 null bits and 12 data bits (MSB first). During a conversion, the data is

outputted on the falling edges of SCLK and is valid on the rising edges.

7

SCLK

Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.

Power Supply input. A voltage source between 4.5V and 5.5V must be applied to this input.

8

VA

VA must be decoupled to GND with a ceramic capacitor value of 0.1 µF in parallel with a

bulk capacitor value of 1.0 µF to 10 µF.

2

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