TMP105 datasheet(12/21 Pages) TI2

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SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(BUF)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

Frame1Two-WireSlaveAddressByte

Frame2PointerRegisterByte

Frame4DataByte2

StartBy

Master

ACKBy

TMP105

ACKBy

TMP105

ACKBy

TMP105

StopBy

Master

Frame3DataByte1

ACKBy

TMP105

SDA

(Continued)

SCL

(Continued)

SDA

SCL

R/W

TMP105

SLLS648D

– FEBRUARY 2005 – REVISED SEPTEMBER 2011

www.ti.com

Table 12. Timing Diagram Definitions for the TMP105

FAST MODE

PARAMETER

UNITS

MIN

MAX

SCL Operating Frequency

f(SCL)

400

kHz

Bus Free Time Between STOP and START Condition

t(BUF)

600

Hold time after repeated START condition.

t(HDSTA)

100

After this period, the first clock is generated.

Repeated START Condition Setup Time

t(SUSTA)

100

STOP Condition Setup Time

t(SUSTO)

100

Data Hold Time

t(HDDAT)

Data Setup Time

t(SUDAT)

100

SCL Clock LOW Period

t(LOW)

1300

SCL Clock HIGH Period

t(HIGH)

600

Clock/Data Fall Time

300

Clock/Data Rise Time

300

1000

for SCLK

≤ 100kHz

TWO-WIRE TIMING DIAGRAMS

Figure 4. Two-Wire Timing Diagram

Figure 5. Two-Wire Timing Diagram for TMP105 Write Word Format

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