SLAS365 datasheet(28/56 Pages) TI2

28 / 56 page

3–16

Master FS

DIN

Master

Slave2

Slave1

Slave0

Master

Slave2

Slave1

Slave0

Master

Slave2

Slave1

Slave0

Write

Command

Reg Addr (D15–D13)

R/W (D12)

Broadcast (D11)

D10–D8

001(1)

111

010(2)

111

100(4)

111

110(6)

111

Data Frame

Control Frame

Time Slot

NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1, Reg.2, Reg.4, and Reg.6 in all

4 DSP codecs (Master, Slave2, Slave1, and Slave0) shown in Figure 3–8. These registers are programmed during the same frame.

Figure 3–20. Broadcast Register Write Example

3.9.4

Bits D15 through D13 represent the control register address that is written with data carried in D7 through D0. Bit D12

determines a read or a write cycle to the addressed register. When D12 = 0, a write cycle is selected. When

D12 = 1, a read cycle is selected. Bit D11 controls the broadcast mode as described above, in which the broadcast

mode is enabled if D11 is set to 1. Always write 1s to bits D10 through D8.

Table 3–3 shows the register map.

Table 3–3. Register Map

D15

D14

D13

D12

D11

D10

Control Register Content

Table 3–4. Register Addresses

D15

D14

D13

No operation

control 1

control 2

control 3

control 4

control 5

control 6

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