TLC5905

LED DRIVER

SLLS401 – NOVEMBER 1999

13

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

shift register latch for gray scale data

The shift register latch for gray scale data is set as a 64 x 1 bit configuration in the 8-bit mode, and as a 128

x 1 bit configuration in the 16-bit mode. The gray scale data, configured as 8 bits, represents the time when

constant current output is being turned on, and the data range is 0 to 255 (00h to FFh). When the gray scale

data is 0, the time is shortest, and the output is not turned on(light off). On the other hand, when the gray scale

data is 255, the time is longest, and it turns on during time of 255 clocks from GSCLK. The configuration of shift

register and latch for gray scale data is shown in Figure 3.

(8 bits)

OUT15 Data

XLATCH

Latch for Gray Scale Data

MSB

128

121

SOUT

Shift Register for Gray Scale Data

SIN

SCLK

16 Bit Mode (MODE=H, RSEL0 and RSEL1=L)

(8 bits)

OUT14 Data

(8 bits)

OUT1 Data

(8 bits)

OUT0 Data

120

113

16

9

LSB

8

0

. . . . . . . . . .

. . . . . . . . . .

(8 bits)

OUT15,14 Data

XLATCH

Latch for Gray Scale Data

MSB

64

57

SOUT

Shift Register for Gray Scale Data

SIN

SCLK

8 Bit Mode (MODE=L, RSEL0 and RSEL1=L)

(8 bits)

OUT13,12 Data

(8 bits)

OUT3,2 Data

(8 bits)

OUT1,0 Data

56

49

16

9

LSB

8

0

. . . . . . . . . .

. . . . . . . . . .

Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data